In order to perform high-speed data communications for transceivers in a Large-Scale Integrated circuit (LSI) or between LSIs, the transmitter converts parallel data into serial data through parallel-serial conversion and the receiver performs serial-parallel conversion on the received serial data so as to generate parallel data. LSIs having a transceiver circuit are provided with a serializer, which performs serial-parallel conversion, and a deserializer, which performs parallel-serial conversion.
In parallel-serial conversion, data is transferred between a plurality of multiplexers (MUXs) in order to convert parallel data into serial data.
Higher speeds of clocks have been making it difficult to transfer data between MUXs with clock transfer. In particular, it has become difficult to properly perform data transfer to a two-input one-output MUX that uses the fastest clock in a transmission circuit.
A technique is known in which the phase of data output from the data transmission unit and the phase of the clock that defines the timing at which the data reception unit receives the data are compared so that the data transmission unit adjusts, on the basis of the comparison result, the phase of the clock that defines the timing at which the data transmission unit transmits data (see for example Patent Document 1).
Conventional timing adjustment circuits do not check whether or not the reception side is receiving data properly. This causes a problem wherein timing adjustment does not always guarantee proper data reception.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2007-82147
[Patent Document 2] Japanese Laid-open Patent Publication No. 58-56553